Variation-Aware Die-to-Die Bonding in Circuit-Partitioned 3D Integrated Circuits

Three-dimensional (3D) technology is considered to be one of the most promising solutions to overcome the interconnect scaling problem, in which multiple planar device layers are bonded together using through-silicon vias (TSVs) [1]. For 3D integration, an IC can be partitioned in three granularities, i.e., technology, architecture and circuit levels [2, 3]. For a circuit partitioned 3D IC, individual circuits are splitted and different gates in a logic block can be placed on different layers. 3D chips can be built in three ways, i.e., wafer-to-wafer (W2W), die-to-wafer (D2W) and die-to-die (D2D) bonding. Without “known good die ” information, the yield of 3D chips can be quite low. Current research work of 3D bonding mainly focuses on the functionality of a circuit, i.e., stacking functional dies to build a functional 3D chip, while timing-related errors are not addressed. The performance of a circuit depends on th