Efficient Design of Check Circuit to detect Multiple Cell Errors in Reversible Logic Synthesis

Abstract—Online Testability is used to detect bit error of Reversible Circuit at runtime using Check circuit to propagate all errors into single line. In this paper, we propose an improved design of check circuit, Modified Test Cell (MTC) can detect error in short time and also able to identify affected cell(s) simultane-ously. We also present a cost effective design of Online Testable Ripple Carry Adder (RCA) with proposed MTC. Proposed design of check circuit is able to enhance the reusability of circuit by replacing corresponding faulty cell(s). I