Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image

Abstract—This paper presents the design and the VLSI imple-mentation of an asynchronous cellular logic array for fast binary image processing. The proposed processor array employs trigger-wave propagation and collision detection mechanisms for binary image skeletonization, and Voronoi tessellation. Low power, low area, and high processing speed are achieved using full custom dy-namic logic design. The prototype array consisting of 64 96 cells is fabricated in a standard 90 nm CMOS technology. The experi-mental results confirm the fast operation of the array, capable of extracting up to skeletons per second, consuming less than 1 nJ/skeleton. The asynchronous operation enables circular wave contours, which improves the quality of the extracted skele-tons. The proposed asynchronous processing module consists of 24 MOS transistors and occupies area. Such array can be used as a co-processing unit aiding global binary image processing in standard pixel-parallel SIMD architectures in vision chips. Index Terms—Cellular processor array, CMOS, CNN, image processing, skeletonization, trigger-wave propagation, vision chips. I