IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs

Abstract — Modern SRAM-based field-programmable gate arrays (FPGAs) are prone to single event upsets compared to application-specific integrated circuits. We propose a synthesis-based in-place x-filling algorithm by utilizing don’t cares to augment the reliability of FPGA-based designs. Compared to circuit- and architecture-based solutions, our algorithm is in place, and does not incur area, power, performance, and design time overheads. Compared to other synthesis-based algorithms, we take into account widely accepted interconnect architecture. For the 10 largest combinational MCNC benchmark circuits mapped to 6-LUT architecture, our approach achieves up to 37 % greater failure rate reduction, and up to 7 × runtime speedup, compared to the best known synthesis-based in-place algorithm, namely the in-place decomposition algorithm. Index Terms — Design reliability, field-programmable gate array (FPGA), in place, interconnect, single event upset (SEU), synthesis, x-filling. I