Heterogeneous-Reliability Memory: Exploiting Application-Level Memory Error Tolerance

Recent studies estimate that server cost contributes to as much as 57 % of the total cost of ownership (TCO) of a data-center [1]. One key contributor to this high server cost is the procurement of memory devices such as DRAMs, especially for data-intensive datacenter cloud applications that need low latency (such as web search, in-memory caching, and graph traversal). Such memory devices, however, may be prone to hardware errors that occur due to unintended bit flips during device operation [40, 33, 41, 20]. To protect against such er-rors, traditional systems uniformly employ devices with high-quality chips and error correction techniques, both of which increase device cost. At the same time, we make the obser-vations that 1) data-intensive applications exhibit a diverse spectrum of tolerance to memory errors, and 2) traditional one-size-fits-all memory reliability techniques are inefficien