Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach

DRAM vendors provide pessimistic current measures in mem-ory datasheets to account for worst-case impact of process variations and to improve their production yield, leading to unrealistic power consumption estimates. In this paper, we first demonstrate the possible effects of process variations on DRAM performance and power consumption by performing Monte-Carlo simulations on a detailed DRAM cross-section. We then propose a methodology to empirically determine the actual impact for any given DRAM memory by assess-ing its performance characteristics during the DRAM cali-bration phase at system boot-time, thereby enabling its opti-mal use at run-time. We further employ our analysis on Mi-cron’s 2Gb DDR3-1600-x16 memory and show considerable over-estimation in the datasheet measures and the energy estimates (up to 28%), by using realistic current measures for a set of MediaBench applications. 1