Simulation and Verification Methodology of Mixed Signal Automotive ICs

The Universal Verification Methodology standard provides immense advanced automatic techniques to the digital verification world. In fact without mechanisms like constraint random stimulus generation, functional coverage and self-checking testbenches, func-tional verification of today’s complex integrated circuits is not conceivable. While digital verification benefits from all these modern methods, analog verification is still a manual process. This report presents a new verification approach which simulates mixed-signal designs through utilizing sophisticated methods used in digital verification. The developed ver-ification technique in this work makes it possible to simulate a DUT with both digital and analog interfaces using event driven simulators. This method is compatible with existing digital verification techniques. The aimed device under test (DUT) contains register transfer level (RTL) and real number model (RNM) blocks. As transaction level modeling affects digital verification to a great extent, analog trans-action level modeling is exploited in this work to achieve more facile strategies in chal