Abstract. In hard real-time systems, where system complexity meets stringent timing constraints, the task of system-level synthesis has become more and more challenging. As a remedy, we introduce an SMT-based system synthesis approach where the Boolean solver determines a static binding of computational tasks to computing resources and a routing of messages over the interconnection network while the theory solver computes a global time-triggered schedule based on the Boolean solver’s solution. The binding and routing is stated as an optimization problem in order to refine the solution found by the Boolean solver such that the theory solver is more likely to find a feasible schedule within a reasonable amount of time. In this paper, we enhan...
Abstract—Task assignment and subsequent schedule synthesis in distributed real time systems is a pro...
Abstract—Time-Triggered Network-on-Chip (TTNoC) is a net-working concept aiming at providing both pr...
In this paper, we consider system- level synthesis as the problem of optimally mapping a task-level...
International audienceWe propose an SMT-based system synthesis approach where the logic solver perfo...
Abstract—We propose an SMT-based system synthesis ap-proach where the logic solver performs static b...
Deciding binding, routing, and scheduling within system synthesis for hard real-time systems can be ...
Real-time system is playing an important role in our society. For such a system, sensitivity to timi...
In Ethernet-based time-triggered networks, like TTEther-net, a global communication scheme, for whic...
Hardware Synthesis is the process by which system-level, Register Transfer (RT) level or behavioral ...
Heuristics are widely used for solving computational intractable synthesis problems. However, until ...
Real-time system is playing an important role in our society. For such a system, sensitivity to timi...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
Synthesis of time-triggered network schedules is a known practice to obtain low jitter and bounded e...
In a real-time system, tasks are required to be completed before their deadlines. Under normal workl...
This paper describes a technique to integrate the three major tasks of high-level synthesis (schedul...
Abstract—Task assignment and subsequent schedule synthesis in distributed real time systems is a pro...
Abstract—Time-Triggered Network-on-Chip (TTNoC) is a net-working concept aiming at providing both pr...
In this paper, we consider system- level synthesis as the problem of optimally mapping a task-level...
International audienceWe propose an SMT-based system synthesis approach where the logic solver perfo...
Abstract—We propose an SMT-based system synthesis ap-proach where the logic solver performs static b...
Deciding binding, routing, and scheduling within system synthesis for hard real-time systems can be ...
Real-time system is playing an important role in our society. For such a system, sensitivity to timi...
In Ethernet-based time-triggered networks, like TTEther-net, a global communication scheme, for whic...
Hardware Synthesis is the process by which system-level, Register Transfer (RT) level or behavioral ...
Heuristics are widely used for solving computational intractable synthesis problems. However, until ...
Real-time system is playing an important role in our society. For such a system, sensitivity to timi...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
Synthesis of time-triggered network schedules is a known practice to obtain low jitter and bounded e...
In a real-time system, tasks are required to be completed before their deadlines. Under normal workl...
This paper describes a technique to integrate the three major tasks of high-level synthesis (schedul...
Abstract—Task assignment and subsequent schedule synthesis in distributed real time systems is a pro...
Abstract—Time-Triggered Network-on-Chip (TTNoC) is a net-working concept aiming at providing both pr...
In this paper, we consider system- level synthesis as the problem of optimally mapping a task-level...