COVER FE ATURE Matthew Schuchhardt

A large fraction of on-chip multicore inter-connect traffic originates not from actual data transfers but from communication between the cores to maintain data coher-ence. Co-locating directories near their shared data eliminates many interconnect traversals, substantially reducing power and energy consumption. T o combat increasing on-chip wire delays as core counts and cache sizes grow, multicore architec-tures have become more distributed. For example, in Intel Xeon Phi and Tilera TILE-Gx processors, the on-chip last-level cache is divided into multiple cache slices that are spread across the die area along with the cores.1 To facilitate data transfers and communication among the cores, such processors employ elaborate on-chip interconnection networks that consume 10 to 28 percent of a multicore chip’s power,2,3 stressing an alread