FASTrust: Feature Analysis for Third-Party IP Trust Verification

Abstract—Third-party intellectual property (3PIP) cores are widely used in integrated circuit designs and it is essential to ensure their trustworthiness. Existing hardware trust verifica-tion techniques suffer from high computational complexity, low extensibility, and inability to detect implicitly-triggered hardware trojans (HTs). To tackle the above problems, in this paper, we present a novel 3PIP trust verification framework, namely FASTrust, which conducts HT feature analysis on the flip-flop level control-data flow graph (CDFG) of the circuit. FASTrust is not only able to identify existing explicitly-triggered and implicitly-triggered HTs appeared in the literature in an efficient and effective manner, but more importantly, it has the unique advantage of being scalable to defend against future and more stealthy HTs by adding new features to the system. Index TermsHardware Trojan, third-party intellectual prop-erty, feature analysis, hardware security I