An Alternative FPGA Implementation of Decoders for Quasi-Cyclic LDPC Codes

Abstract — Due to their Shannon-limit-approaching performance and low-complexity decoding, low-density parity-check (LDPC) codes have been used for forward error correction in a broad-range of communication and storage systems. In addition to its low-complexity, the iterative decoding algorithm used for decoding LDPC codes is inherently parallel. To exploit the parallelism at a larger extent, a significant amount of research has been directed toward field-programmable gate-array (FPGA) implementation of LDPC decoders in recent years. In this paper, we propose an alternative FPGA implementation of decoders for quasi-cyclic LDPC codes based on MitrionC hardware programming language. We explain basic implementation steps using an example of a quasi-cyclic LDPC code particularly suited to optical communication and magnetic recording systems. We provide FPGA results and compare them against the traditional software simulation results