Virtual Execution Platforms for Mixed-Time-Criticality Systems: The CompSOC Architecture and Design Flow∗

Systems on chip (SOC) contain multiple concurrent appli-cations with different time criticality (firm, soft, non real-time). As a result, they are often developed by different teams or companies, with different models of computation (MOC) such as dataflow, Kahn process networks (KPN), or time-triggered (TT). SOC functionality and (real-time) performance is verified after all applications have been inte-grated. In this paper we propose the CompSOC platform and de-sign flows that offers a virtual execution platform per appli-cation, to allow independent design, verification, and execu-tion. We introduce the composability and predictability con-cepts, why they help, and how they are implemented in the different resources of the CompSOC architecture. We de-fine a design flow that allows real-time cyclo-static dataflow (CSDF) applications to be automatically mapped, verified, and executed. Mapping and analysis of KPN and TT ap-plications is not automated but they do run composably in their allocated virtual platforms. Although most of the techniques used here have been pub-lished in isolation, this paper is the first comprehensive overview of the CompSOC approach. Moreover, three new case stud-ies illustrate all claimed benefits: 1) An example firm-real-time CSDF H.263 decoder is automatically mapped and ver-ified. 2) Applications with different models of computation (CSDF and TT) run composably. 3) Adaptive soft-real-time applications execute composably and can hence be verified independently by simulation. 1