1Ultra-low-power processing array for image enhancement and edge detection

Abstract—This paper presents a massively parallel processing array designed for the 0.13µm 1.5V standard CMOS base process of a commercial 3-D TSV stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be turned into anisotropic by a very simple voltage comparator between neighboring nodes whose output controls the gate of the elementary MOS resistor. Anisotropic diffusion enables image enhancement by removing noise and small local variations while preserving edges. A binary edge image can be also attained by combining the output of the voltage comparators. In addition to these processing capabilities, the simulations have confirmed the robustness of the array against process variations and mismatch. The power consumption extrapolated for a VGA-resolution array processing images at 30fps is 570µW. Index Terms—Diffusion, RC network, Gaussian filtering, anisotropic filtering, resistive fuse, low-power, voltage comparato