Design considerations for interleaved ADCs

Abstract—Interleaving can relax the power-speed tradeoffs of analog-to-digital converters and reduce their metastability error rate while increasing the input capacitance. This paper quantifies the benefits and derives an upper bound on the per-formance by considering noise and slewing requirements of the circuit driving the system. A frequency-domain analysis of interleaved converters is also presented that sheds light on the corruption mechanisms due to interchannel mismatches. A background timing mismatch calibration technique is proposed and experimentally shown to reduce the image to dB for input frequencies exceeding 500 MHz. Index Terms—Background calibration, flash analog-to-digital converters (ADCs), figure of merit, image, interleaving mis-matches, low-power ADCs, pipelined ADCs, SAR ADCs, timing mismatch