Abstract—The memory bandwidth can dramatically be improved by means of stacking the main memory (DRAM) on processor cores and connecting them by wide on-chip buses composed of through silicon vias (TSVs). The 3D stacking makes it possible to reduce the cache miss penalty because large amount of data can be transferred from the main memory to the cache at a time. If a large cache line size is employed, we can expect the effect of prefetching. However, it might worsen the system performance if programs do not have enough spatial localities of memory references. To solve this problem, we introduce software-controllable variable line-size cache scheme. In this paper, we apply it to an L1 data cache with 3D stacked DRAM organization. In our eval...
Resource pooling, wheremultiple architectural components are shared among cores, is a promising tech...
Memory bandwidth has become a major performance bottleneck as more and more cores are integrated ont...
Abstract—As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high ...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
Abstract — This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-...
This paper proposes a novel cache architecture suit-able for merged DRAM/logic LSIs, which is called...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
Intelligent Memory Systems: Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12...
Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
Process variations in integrated circuits have significant impact on their performance, leakage and ...
Abstract—This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memo...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called ...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called ...
International audienceWith the emergence of manycore architectures, the need of on-chip memories suc...
Resource pooling, wheremultiple architectural components are shared among cores, is a promising tech...
Memory bandwidth has become a major performance bottleneck as more and more cores are integrated ont...
Abstract—As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high ...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
Abstract — This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-...
This paper proposes a novel cache architecture suit-able for merged DRAM/logic LSIs, which is called...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
Intelligent Memory Systems: Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12...
Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
Process variations in integrated circuits have significant impact on their performance, leakage and ...
Abstract—This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memo...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called ...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called ...
International audienceWith the emergence of manycore architectures, the need of on-chip memories suc...
Resource pooling, wheremultiple architectural components are shared among cores, is a promising tech...
Memory bandwidth has become a major performance bottleneck as more and more cores are integrated ont...
Abstract—As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high ...