A SIMD cellular processor array vision chip with asynchronous processing capabilities. IEEE Transactions [12) [13) [14) on Circuits and Systems I: Regular Papers, 2011(99): p. DOl 10.1 109/TCSI.201 1.2131370

Abstract—This paper describes an architecture and implemen-tation of a digital vision chip that features mixed asynchronous/ synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of op-eration: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global op-erations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 22 proof-of-concept array has been man-ufactured in 0.35 m CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably com-pares with other digital and analog vision chips. The results of low-and medium-level image processing on the chip are presented. Index Terms—Asynchronous image processing, cellular pro-cessor array, smart sensor, vision chip. I