IEEE TRANS. ON INSTRUM. MEAS. 1 An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems

Abstract—The most popular representative devices of re-configurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse the same hardware for different tasks at dif-ferent phases of an application execution. Moreover, the tasks can be swapped on the fly while part of the hardware continues to operate. This is known as dynamic reconfigura-tion and evaluation of its performance presents interesting research challenges. This paper introduces a general frame-work to measure the reconfiguration time from the system perspective. In addition, a methodology to setup different system parameters, gather and process automatically the experimental results has been developed. It is proven that these parameters affect applications designed in a dynam-ically reconfigurable system, and rapid evaluation enables the quick examination of their impact on performance. Re-sults demonstrate the usefulness of the framework. Index Terms—Dynamic reconfiguration, Partial reconfig-uration, Field programmable gate arrays, Reconfigurable architectures, System analysis and design, Measurement I