Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code

Abstract—Phase change memory (PCM) has emerged as a mostly promising non-volatile memory. Multi-level Cell (MLC) PCM that stores multiple bits in a single cell, has the benefits of increasing capacity and lower cost-per-bit. However, as feature size scales down, prior work reports that low frequency noise and random telegraph noise would greatly jeopardize the reliability of MLC PCM. In this paper, we firstly analyze the multi-bit error rate induced by noise and then propose a multi-bit ECC (Error Correction Code) to alleviate the deleterious noise effects in MLC PCM. As far as we know, this is the first paper to utilize of error correction method to mitigate the impact of noise at architectural level. However, a strong multi-bit ECC requires additional storage and latency. Thus, we propose a 6EC-7ED BCH scheme which achieves a tradeoff between correction capability and overhead. Compared to conventional DRAM ECC, this scheme effectively improves the reliability of MLC PCM system, while has the comparable storage overhead. Moreover, the experimental results show this scheme incurs negligible latency cost with merely 1% performance degradation. Keywords-MLC PCM; reliability; noise; soft error; ECC I