Design and Experimental Verification of a Power

Abstract—This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. The solution doubles the optimal speed of operation of the SAR ADCs at the relative low power cost of a low-resolution Flash. The digital correction method and a capacitor-based DAC ensure nondemanding requirements for the Flash. The effectiveness of the architecture is verified in a 90-nm CMOS chip whose active core area is 0.64 mm2. The ADC obtains a peak SNDR of 51.8 dB and SFDR of 63.4 dB at 90 MS/s consuming 13.5 mW from a 0.9-V supply. Measured DNL and INL are 0.87 LSB and 1.55 LSB, respectively. Index Terms—Analog-to-digital converter (ADC), digital error correction (DEC), Flash ADC, SAR ADC, subranging ADC