A 1 Mb/s – 40 Mb/s WBS Transceiver for Human Body Channel Communication

In this paper, we present a low-power, high-speed and large jitter tolerance wideband signaling (WBS) transceiver for human body channel communication (BCC). The proposed WBS transceiver sends data with a spread spectrum clock generator (SSCG) to reduce electromagnetic emission. In order to improve the jitter tolerance of the receiver, we propose an add-drop FIFO algorithm with a blind oversampling clock and data recovery (CDR) circuit to recover the corrupted clock and data. The proposed WBS transceiver is implemented in a standard performance 90nm CMOS process, and the core area is 0.15mm2. The data rate of the proposed transceiver ranges from 1-Mb/s to 40-Mb/s. The power consumption is 1.64mW at 40-Mb/s and the bit energy is 0.041nJ/b. 1