lucent.com

paristech.fr Recent work motivates the design of Information-centric rou-ters that make use of hierarchies of memory to jointly scale in the size and speed of content stores. The present paper ad-vances this understanding by (i) instantiating a general pur-pose two-layer packet-level caching system, (ii) investigat-ing the solution design space via emulation, and (iii) intro-ducing a proof-of-concept prototype. The emulation-based study reveals insights about the broad design space, the ex-pected impact of workload, and gains due to multi-threaded execution. The full-blown system prototype experimentally confirms that, by exploiting both DRAM and SSD memory technologies, ICN routers can sustain cache operations in excess of 10Gbps running on off-the-shelf hardware