A 6-b 1.6-GS/s ADC with redundant cycle one-tap embedded DFE in 90-nm CMOS

Abstract—ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embed-ding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or de-creasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm area. Index Terms—Analog-to-digital converter (ADC), ADC-based receiver, decision feedback equalizer (DFE), embedded equaliza-tion, successive approximation register (SAR), time interleaving. I