FaCSim: A Fast and Cycle-Accurate Architecture Simulator for Embedded Systems ∗

There have been strong demands for a fast and cycle-accurate vir-tual platforms in the embedded systems area where developers can do meaningful software development including performance de-bugging in the context of the entire platform. In this paper, we de-scribe the design and implementation of a fast and cycle-accurate architecture simulator called FaCSim as a first step towards such a virtual platform. FacSim accurately models the ARM9E-S proces-sor core and ARM926EJ-S processor’s memory subsystem. It accu-rately simulates exceptions and interrupts to enable whole-system simulation including the OS. Since it is implemented in a modular manner in C++, it can be easily extended with other system compo-nents by subclassing or adding new classes. FaCSim is based on an interpretive simulation technique to provide flexibility, yet achiev-ing high speed. It enables fast cycle-accurate architecture simula