DSP Processor/Compiler CO-Design: A Quantitative Approach

In the paper the problem of processor/compiler co-design for digital signal processing and embedded SY-stems is discussed. The main principle we follow is the top-down approach characterized by extensive simula-tion and quantitative performance evaluation of proces-sor and compiler. Although well established in the de-sign of state-of-the-art general purpose processors and compilers, this approach is rarely followed by leading producers of signal and embedded processors. A s a con-sequence, the matching between the processor and the compiler i s low. In the paper we focus on three main components of our exploration environment- bench-marking methodology (DSPstone), fast processor simu-lation (SuperSim), and machine description (LISA). Most of the paper is devoted to the technique of compi-led processor simulation. The speedup obtained allows an exploration of a much larger design space than it was possible with standard processor simulators. 1