Noname manuscript No. (will be inserted by the editor) Understanding the Limitations and Improving the Relevance of SPICE Simulations in Side-Channel Security Evaluations

Abstract Simulation is a very powerful tool for hard-ware designers. It generally allows the preliminary eval-uation of a chip's performance before its final tape out. As security against side-channel attacks is an increas-ingly important issue for cryptographic devices, simu-lation also becomes a desirable option for preliminary evaluation in this case. However, its relevance highly depends on the proper modeling of all the attack pecu-liarities. For example, several works in the literature directly exploit SPICE-like simulations without con-sidering measurement peripherals. But the outcome of such analyses may be questionable, as witnessed by the recent results of Renauld et al. at CHES 2011, which showed how far the power traces of an AES S-box implemented using a dynamic and differential logic style fabricated in 65nm CMOS can lie from their post-layout simulations. One important difference was found in the linear dependencies between the (simulated and actual) traces and the S-box input/output bits. While simulations exhibited highly non-linear traces, actual measurements were much more linear. As linearity is a crucial parameter for the application of non-profiled side-channel attacks (which are only possible under th