H2A: A Hardened Asynchronous Network on Chip

Abstract — One of the next challenges for asynchronous com-munication architectures is reliability, in the form of robustness to single event effects, when under the impact of particles gener-ated by ionizing radiation. This occurs because technology down-scaling continuously increases the logic sensitivity of silicon de-vices to such effects. Contrary to what happens in synchronous circuits, delay variations induced by radiation usually have no impact on asynchronous quasi-delay insensitive combinational logic blocks, but in storage devices, bit flips may corrupt the circuit state with no recovery solution, even when using asyn-chronous circuits. This work proposes a new set of hardening techniques against single event effects applicable to asynchronous networks-on-chip. It presents practical case studies of use for these techniques and evaluates them in close to real life situa-tions. Obtained results show that the achieved increase in asyn-chronous network-on-chip robustness has the potential to leve-rage this communication architecture solution as the main choice for the next generations of complex silicon devices on advanced nodes technologies such as 32 nm, 28 nm and below. Keywords—asynchronous circuits; networks on chip; soft error; single event effect I