CSHARP: Coherence and SHaring Aware Replacement Policies for Parallel Applications

Abstract—Parallel applications are becoming mainstream and architectural techniques for multicores that target these applications are the need of the hour. Sharing of data by multiple threads and issues due to data coherence are unique to parallel applications. We propose CSHARP, a hardware framework that brings coherence and sharing awareness to any shared last level cache replacement policy. We use the degree of sharing of cache lines and the information present in coherence vectors to make replacement decisions. We apply CSHARP to a state-of-the-art cache replacement policy called TA-DRRIP to show its effectiveness. Our experiments on four core simulated system show that applying CSHARP on TA-DRRIP gives an extra 10 % reduction in miss-rate at the LLC. Compared to LRU policy, CSHARP on TA-DRRIP shows a 18 % miss-rate reduction and a 7 % performance boost. We also show the scalability of our proposal by studying the hardware overhead and performance on a 8-core system