Robust Low-Power Reconfigurable Computing with a Variation-Aware Preferential Design Approach

Abstract—Reconfigurable hardware platforms, such as Field Pro-grammable Gate Arrays (FPGA), are being increasingly used in diverse embedded applications. These platforms often use high-density memory array, which suffer from variation-induced parametric failures. Such failures lead to incorrect operation and hence, loss in output quality for many signal processing applications. In this paper, we propose a preferential design approach at both application mapping and circuit level, which can significantly improve output quality as well as energy efficiency for signal processing applications under large parameter variations. The proposed mapping process considers the reliability map of a memory array and maps the important operations with respect to output quality to more reliable memory blocks under performance constraint. At circuit level, we exploit the read-dominant memory access pattern in reconfigurable platforms to skew the memory cells for better read stability leading to improved quality. Such an architecture/circuit co-design approach can also tolerate increased failure rate at low operating voltage, thus facilitating low-power operation. Index Terms—Reconfigurable computing, FPGA, MBC, spatio-temporal mapping, reliability, low power, preferential design