Meeting Exascale Interconnect Requirements with Integrated Photonics

already exist and run on Petascale class Supercomputers [1]. Modelers, programmers, and computer architects alike thus already look at the next grand challenge: build an Exaflops (1018) capable Supercomputer, and develop simulation codes able to effectively leverage this computing power. Neither the clock speed nor complexity of processors will progress much in the next years (as they have not progressed in the last years). The Exascale mark will thus mainly be attained by mean of parallelism increase. An Exascale machine will roughly require 100 millions of processors (108) each capable of roughly 10 Gigaflops (1010). This is ~30 times more than the three millions of core active in today’s most powerful SuperComputer, Tianhne-2. Some of this parallelism will be “absorbed ” by multi-core architectures: Intel’s Knights Corner included in Tianhne-2 involves 50 cores on the same chip, yielding around 1 Teraflop. Upcoming chips will likely deliver 10-30 Teraflops. However, from 30 to 100 thousands of these inflated chips will still be necessary to obtain an Exaflops. Massive interconnects regrouping up to 100K end-points, capable of ultra-short latencies, and delivering ultra-high bandwidth will thus be required [2]. Scaling current interconnects is, however, a challenge in itself. In the last ten years, the bandwidths of Supercomputer interconnect sluggishly evolved from around 10 Gbps to 100 Gbps. Signaling rates have been with difficulty multiplied by a factor of 5, from 5 to 25 Ghz [3]. As for processor clock frequencies, CMO