Abstract — A fully-digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally-controlled oscillator that deliberately avoids any ana-log tuning controls. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in a digital deep-submicron CMOS process, the proposed architecture is more advantageous over conventional charge-pump-based PLL’s since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this paper, we present new techniques for achieving amplitude control of the RF output. Thi...
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct ...
This paper describes the design and implementation of a low power IF frequency synthesizer which can...
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS...
Traditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applicatio...
We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry...
The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital ci...
It has been a constant challenge in wireless system design to meet the growing demand for an ever hi...
An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achi...
The fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conven...
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct d...
Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL...
ESSCIRC 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14 - 18 Septe...
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS...
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct ...
This paper describes the design and implementation of a low power IF frequency synthesizer which can...
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS...
Traditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applicatio...
We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry...
The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital ci...
It has been a constant challenge in wireless system design to meet the growing demand for an ever hi...
An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achi...
The fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conven...
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct d...
Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL...
ESSCIRC 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14 - 18 Septe...
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS...
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct ...
This paper describes the design and implementation of a low power IF frequency synthesizer which can...
RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS...