A Novel Delay Fault Testing Methodology Using On-Chip Low-Overhead Delay Measurement Hardware at Strategic

Abstract—A novel integrated approach for delay-fault testing in external (automatic-test-equipment-based) and test-per-scan built-in self-test (BIST) using on-die delay sensing and test point insertion is proposed. A robust, low-overhead, and process-tolerant on-chip delay-sensing circuit is designed for this purpose. An algorithm is also developed to judiciously insert delay-sensor circuits at the internal nodes of logic blocks for improving delay-fault coverage with little or no impact on the critical-path delay. The proposed delay-fault testing approach is verified for tran-sition- and segment-delay-fault models. Experimental results for external testing (BIST) show up to 31 % (30%) improvement in fault coverage and up to 67.5 % (85.5%) reduction in test length for transition faults. An increase in the number of robustly de-tectable critical-path segments of up to 54 % and a reduction in test length for the segment-delay-fault model of up to 76 % were also observed. The delay and area overhead due to insertion of the delay-sensing hardware have been limited to 2 % and 4%, respectively. Index Terms—Built-in delay sensor (BIDS), built-in self-test (BIST), delay fault testing, segment delay fault, test point inser-tion, transition delay fault. I