A Macro Generator for Arithmetic Cores

In this paper we present a tool for macro generation of soft cores performing arithmetic operations for a wide variety of operand sizes and architectures. The tool produces structural Verilog descriptions. Hence, any commercial synthesis tool can be used to map the produced designs to a specific technology. The generator covers all four basic operations: addition, subtraction, multiplication and division. Therefore, applications requiring arithmetic cores, as for example digital signal processing and multimedia applications, can be completed faster and with less effort. 1