A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications

Abstract- A 1.056 GS/s, 5-bit/6-bit switchable flash analog-to- ADC which can adapt its resolution according to the system's digital converter (ADC) is designed in 0.18-gm CMOS, which dynamic operation mode and to optimize the power utilization. is suitable to be used in an OFDM-UWB transceiver. A With 1.056 GS/s sampling frequency and an ENOB of 4.2 bits and resolution switchable structure is proposed to optimize power 5.0 bits, respectively, at an input signal frequency of 413 MHz, the consumption according to the dynamic requirement of the ADC fulfils the different data rates requirements of the MB-OFDM application. Two-stage interpolation and averaging techniques system. Due to its large ERBW different receiver topologies can be are employed to average the offset of the preamplifiers. Monte supported. However, the proposed ADC will not be limited to only Carlo simulation results show that the proposed ADC achieves these applications. 4.2b/5.Ob ENOB in 5-bit/6-bit working modes with a 413-MHz This paper is organized as follows: section II illustrates the flash input signal. The mean value of DNL and INL is 0.32 and 0.56 ADC architecture and the key ideas to improve the linearity and LSB for 5-bit mode, while 0.47 and 0.62 LSB for 6-bit mode. reduce the power consumption. Section III describes and explains The analog part consumes 36 mW and 98 mW from a 1.8-V the circuit implementation of the main building blocks. Finally, in supply in 5-bit and 6-bit operation mode, respectively. section IV simulation results are provided to verify the effectiveness of the design and to demonstrate the performance of the ADC. I