Abstract—Within-die parameter variations can cause wide delay distribution among similar functional units in superscalar processors. Conventionally, the frequency of operation is reduced to accommodate the slowest unit, which in turn degrades throughput. We present a low-overhead design technique that sets the operating frequency in a superscalar processor based on the faster units and allows more cycles for the slower units. We propose an associated priority scheduling strategy to schedule instructions in the functional units to maximize throughput. Simulation results on a set of benchmarks show that, by assigning a higher scheduling priority to faster units, we can achieve 18 percent improvement in performance on average with negligible d...
LaZy Superscalar is a processor architecture which delays the execution of fetched instructions unti...
Super-scalar processors can execute multiple instructions out-of-order per cycle and speculatively ...
Faced with the challenge of finding ways to use an ever-growing transistor budget, microarchitects h...
With increasing parameter variations, functional units (FUs) in a chip experience considerable local...
sors (TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) pe...
The advance in semiconductor technologies presents the serious problem of parameter variations. They...
10th International Symposium on Quality Electronic Design : March 16-18, 2009 : San Jose, CA, USAThe...
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic su...
the 9th International Symposium on Quality Electronic Design (ISQED\u2708) : March 17-19, 2008 : San...
As integrated-circuit technology continues to scale, process variation is becoming an issue that can...
In this paper, we consider the problem of scheduling a set of instructions on a single processor wit...
The foremost goal of superscalar processor design is to increase performance through the exploitatio...
Abstract — As technology scales, the delay uncertainty caused by process variations has become incre...
We consider online scheduling algorithms in the dynamic speed scaling model, where a processor can s...
Abstract—Variation in the CMOS manufacturing processes cause the transistors on each chip to differ,...
LaZy Superscalar is a processor architecture which delays the execution of fetched instructions unti...
Super-scalar processors can execute multiple instructions out-of-order per cycle and speculatively ...
Faced with the challenge of finding ways to use an ever-growing transistor budget, microarchitects h...
With increasing parameter variations, functional units (FUs) in a chip experience considerable local...
sors (TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) pe...
The advance in semiconductor technologies presents the serious problem of parameter variations. They...
10th International Symposium on Quality Electronic Design : March 16-18, 2009 : San Jose, CA, USAThe...
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic su...
the 9th International Symposium on Quality Electronic Design (ISQED\u2708) : March 17-19, 2008 : San...
As integrated-circuit technology continues to scale, process variation is becoming an issue that can...
In this paper, we consider the problem of scheduling a set of instructions on a single processor wit...
The foremost goal of superscalar processor design is to increase performance through the exploitatio...
Abstract — As technology scales, the delay uncertainty caused by process variations has become incre...
We consider online scheduling algorithms in the dynamic speed scaling model, where a processor can s...
Abstract—Variation in the CMOS manufacturing processes cause the transistors on each chip to differ,...
LaZy Superscalar is a processor architecture which delays the execution of fetched instructions unti...
Super-scalar processors can execute multiple instructions out-of-order per cycle and speculatively ...
Faced with the challenge of finding ways to use an ever-growing transistor budget, microarchitects h...