Diminished-1 Modulo 2n+1 Squarer Design

Squarers modulo M are useful design blocks for digi-tal signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2n + 1. To avoid using (n+1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2n + 1 arithmetic applications. In this paper, for the first time in the open lit-erature, we formally derive modulo 2n + 1 squarers that adopt the diminished-1 number system. The resulting im-plementations are built using only full- or half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly. 1