Impacts of Random Telegraph Noise (RTN) on Digital Circuits

Abstract — Random telegraph noise (RTN) is one of the impor-tant dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systemat-ically investigated. Instead of trap occupancy probability under dc bias condition ( pdc), which is traditionally used for RTN characterization, ac trap occupancy probability ( pac), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on pac. The results show that degrada-tions are highly workload dependent and that pac is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design. Index Terms — Bit error rate (BER), dynamic variability, failure probability, Monte Carlo simulation, oxide trap, random telegraph noise (RTN), ring oscillator, signal integrity, SRAM