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In this paper, a fast algorithm having a pseudopolynomial run-time and memory requirement in the worst-case is developed to generate multiplierless architectures at all wordlengths for con-stant multiplications in linear DSP transforms. It is also re-emphasized that indefinitely reducing operators for multiplierless architectures is not sufficient to reduce the final chip area. For a major reduction, techniques like resource folding must be used. Simple techniques for improving the results are also presented. Information About Authors