Boundary value testing is a widely used functional test-ing approach. This paper presents a new boundary value selection approach by applying fault detection rules for in-tegrated circuits. Empirical studies based on Redundant Strapped-Down Inertial Measurement Unit (RSDIMU) of the 34 program versions and 426 mutants compare the new approach to the current boundary value testing methods. The results show that the approach proposed in this paper is remarkably effective in conquering test blindness, reduc-ing test cost and improving fault coverage
The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conduc...
122 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.Finally, we present a diagnos...
The modelling and testing of microelectronic circuits for different technologies are presented. Rapi...
The test technique called "boundary scan test" (BST) offers new opportunities in testing but confron...
AbstractThis paper proposes an extension to the D-algorithm, for integrated circuits described using...
In avionics, like glide computers, the problem of No Faults Found (NFF) is a very serious and extrem...
The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It i...
This thesis is concerned with the practical implications of manufacture testing of loaded printed ci...
With the advances in packaging technologies and increasing demand for high-speed and small size elec...
In this paper we give an overview of recent work in extraction, simulation, and IDDQ test generation...
Increasing complexity of circuit boards and surface mount technology has made it difficult to test t...
Functional tests are developed during design verification to ensure the correctness of design. They ...
Experimental results obtained with the use of measurement reduction for statistical IC fault diagnos...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...
With the advent of VLSI technology, the systems fabricated in deep sub micron technology are more pr...
The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conduc...
122 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.Finally, we present a diagnos...
The modelling and testing of microelectronic circuits for different technologies are presented. Rapi...
The test technique called "boundary scan test" (BST) offers new opportunities in testing but confron...
AbstractThis paper proposes an extension to the D-algorithm, for integrated circuits described using...
In avionics, like glide computers, the problem of No Faults Found (NFF) is a very serious and extrem...
The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It i...
This thesis is concerned with the practical implications of manufacture testing of loaded printed ci...
With the advances in packaging technologies and increasing demand for high-speed and small size elec...
In this paper we give an overview of recent work in extraction, simulation, and IDDQ test generation...
Increasing complexity of circuit boards and surface mount technology has made it difficult to test t...
Functional tests are developed during design verification to ensure the correctness of design. They ...
Experimental results obtained with the use of measurement reduction for statistical IC fault diagnos...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...
With the advent of VLSI technology, the systems fabricated in deep sub micron technology are more pr...
The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conduc...
122 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.Finally, we present a diagnos...
The modelling and testing of microelectronic circuits for different technologies are presented. Rapi...