Field-Based Branch Prediction for Packet Processing Engines

Abstract—Network Processors have exploited all aspects of architecture design, such as employing multi-core, multi-threading and hardware accelerator, to support both the ever-increasing line rates and the higher complexity of network applications. Micro-architectural techniques like superscalar, deep pipeline and speculative execution provide an excellent method of improving performance without limiting either the scalability or flexibility, provided that the branch penalty is well controlled. However, traditional branch predictors are not as efficient in network applications as in general purpose processing, due to the fewer variations in branch patterns of packet processing. To improve the prediction accuracy, we propose a flow-based prediction mechanism which caches the branch histories of packets with similar header fields, since they normally undergo the same execution path. For packets that cannot find a matching entry in the history table, a fallback gshare predictor is used to provide branch direction. Simulation results show that the our scheme achieves an average hit rate in excess of 97.5 % on a selected set of network applications and real-life packet traces, with a similar footprint to the traditional branch predictors used in modern microprocessors. Keywords-branch prediction; network processor; network traffic; packet flow I