Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor

Abstract — Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. However, the increasing circuit size limits the granularity of diagnosis, resulting in large suspect fault list. In this paper, we present a methodology for improving delay fault localization in test-per-scan BIST using on-die delay sensing at selective test points. It is demonstrated that the proposed technique can improve the resolution of fault localization for both transition and segment delay fault models. Experimental results for a set of ISCAS89 benchmarks show upto 49 % (82%) average improvement in fault localization for transition (segment) delay fault models. The area overhead due to delay sensing hardware have been limited to 4%