Microarchitectural Characterization of Irregular Applications on GPGPUs

In recent years, GPGPUs have experienced tremendous growth as general-purpose and high-throughput computing devices. However, irregular applications cannot fully utilize the hard-ware resource because of their plenty of control-flow diver-gences, irregular memory accesses and load imbalances. The lack of in-depth characterization and quantifying the ways in which irregular applications differ from regular ones on GPGPUs has prevented users from effectively making use of the hardware resource. We examine a suite of representative irregular applications on a cycle-accurate GPU simulator. We characterize their performance aspects and analyze the bottlenecks. We also assess the impact of changes in cache, DRAM and interconnect and discuss the implications for G-PU architecture design. This work is useful in understanding and optimizing irregular applications on GPUs