> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1

Abstract—In this paper, three non-volatile flip-flop (NVFF) /SRAM cells that utilize a single MTJ (magnetic tunneling junction) as non-volatile resistive element are proposed. These cells have the same core (i.e. 6T) but they employs different numbers of MOSFETs to implement the so-called ‘instantly on, normally off ’ mode of operation. The additional transistors are utilized for the restore operation to ensure that the data stored in the non-volatile circuitry can be written back into the flip-flop core once the power is made available. These three cells (7T, 9T and 11T) are extensively analyzed in terms of their operations in 32nm technology, such as operational delays (for the write, read and restore operations), the static noise margin (SNM), critical charge and process variations (in both the MOSFETs and the resistive element). Simulation results show that an increase in the number of MOSFETs in the cells causes improvements in critical charge and tolerance to process variations at the expense of an increase in power dissipation. The SNM and the delay of the restore operation however do not necessarily increase with the number of MOSFETs in the cell, but rather on the control of access to the storage nodes from the single MTJ. Index Terms — Non-volatile Flip-flop, magnetic tunneling junction, SRAM, resistive switching I