Congurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

Abstract We describe a fully recongurable low-density par-ity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that ts into the allocated memories while achieving high decoding throughput. Our VLSI implementation has been optimized for the IEEE 802.11n standard and achieves a throughput of 780 Mbit/s with a core area of 3.39 mm2 in 0.18 m CMOS technology. I