Integrating hardware limitations in CAN schedulability analysis

The existing schedulability analysis for the Controller Area Network (CAN) does not take into account that a CAN controller has finite buffer space to store outgoing messages and high priority messages may suffer from pri-ority inversion if the buffers are already occupied by low priority messages. This gives rise to an additional delay for high priority messages, which, if not considered, may result in a deadline violation. In this paper, we explain the cause of this additional delay and extend the exist-ing CAN schedulability analysis to integrate it. Finally, we suggest implementation guidelines that minimizes both the run-time CPU overhead and the additional delay due to priority inversion.