A number of techniques to reduce the cache leakage energy have so far been proposed. However, the low-leakage caches cause performance degradation. In order to solve this performance issue, we propose a new cache management technique. In this approach, a small number of cache lines which are frequently accessed in sleep mode are forced to stay in always-active mode. In this mode, transiting to the sleep mode is prohibited. In our evaluation, this approach can eliminate almost all performance overhead compared to conventional low-leakage cache without affecting the energy efficiency
Technology projections indicate that static power will become a major concern in future generations ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Cool Chips X : the 10th anniversary of IEEE Symposium on Low-Power and High-Speed Chips : April 18-2...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
In the design of embedded systems, especially battery-powered systems, it is important to reduce ene...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
University of Minnesota M.S.E.E. thesis. June 2016. Major: Electrical/Computer Engineering. Advisor:...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
Technology projections indicate that static power will become a major concern in future generations ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Cool Chips X : the 10th anniversary of IEEE Symposium on Low-Power and High-Speed Chips : April 18-2...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
In the design of embedded systems, especially battery-powered systems, it is important to reduce ene...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
University of Minnesota M.S.E.E. thesis. June 2016. Major: Electrical/Computer Engineering. Advisor:...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
Technology projections indicate that static power will become a major concern in future generations ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...