Energy Efficient Code Generation for Processors with Exposed Datapath

In a modern processor architecture the register file (RF) consumes considerable amount of power. Therefore it is im-portant to reduce the RF accesses when designing an energy efficient architecture. It is well-known that with datapath exposed to software, the transport-triggered architectures (TTAs) can substantially reduce the RF traffic. In this pa-per, we analyze the potential of using MOVE-Pro, a TTA-based processor architecture. And we propose the compiler back-end for MOVE-Pro which can generate code that saves energy consumption by performing energy aware instruction scheduling to reduce RF accesses. The proposed architecture and compiler design is flexible. In the experiments we com-pare the proposed architecture with a RISC processor with the same resource, and achieve a reduction of RF accesses by up to 80%, which results in up to 11 % saving in total core power. Meanwhile the dynamic cycle count remains almost the same as the reference processor, which means energy is saved without compromising performance