Improved policies for drowsy caches in embedded processors

In the design of embedded systems, especially battery-powered systems, it is important to reduce energy consump-tion. Cache are now used not only in general-purpose pro-cessors but also in embedded processors. As feature sizes shrink, the leakage energy has contributed to a significant portion of total energy consumption. To reduce the leak-age energy of cache, the Drowsy cache was proposed, in which the cache lines are periodically moved to the low-leakage mode without loss of its content. However, when a cache line in the low-leakage mode is accessed, one or more clock cycles are required to transition the cache line back to the normal mode before its content can be accessed. As a result, these penalty cycles may significantly degrade the cache performance, especially in embedded processors without out-of-order execution. In this paper, we propose four mode transition policies which aim at high energy re-duction with the minimum performance degradation. We also compare our policies with existing policies in the con-text of embedded processors. Experimental results demon-strate the effectiveness of the proposed policies.