Problem of Timing Mismatch in Interleaved ADCs

Time interleaving can relax the speed-power trade-off of analog-to-digital converters but at the cost of sensitivity to interchannel mismatches. This paper addresses the prob-lem of timing mismatch, its detection, and its correction. A new frequency-domain analysis gives insight into the im-pact of the mismatch on random input signals and quan-tifies the resulting noise. A number of timing error cal-ibration techniques are reviewed and a new approach is proposed. I