on Device and SRAM Performance

Abstract — One of the key challenges in scaling beyond 10-nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage, VT, inhibits VCC scaling. In this paper, we present a comprehensive study of process variations and sidewall roughness (SWR) effects in silicon (Si) bulk n-/p-FinFETs, In0.53Ga0.47As bulk n-FinFETs, germanium (Ge) bulk p-FinFETs, and gallium antimonide– indium arsenide (GaSb–InAs) staggered-gap heterojunction n-/p-tunnel FETs (HTFETs) using 3-D Technology Computer Aided Design numerical simulations. According to the sensitivity study, FinFET and tunnel FET (TFET) device parameters are highly susceptible to fin width, WFIN, and ultrathin body thick-ness, Tb, variations, respectively. TFETs show higher variation in device performance than FinFETs. A Monte Carlo study of SWR variation on n- and p-FinFETs shows higher 3σ(VT Lin) of In0.53Ga0.47As bulk n- and Ge bulk p-FinFETs than their Si counterparts. Furthermore, to study the variation impact on memory circuits, we simulate 6T and 10T static random access memory (SRAM) cells with FinFETs and HTFETs, respectively. The probability distribution of read failure in SRAM cells at different supply voltages, VCC, shows that HTFETs require 10T SRAM cell architecture and less than 4 % variation in Tb for their VCCmin to approach 200 mV. Index Terms — III-V compound semiconductors, FinFET, heterojunction tunnel FET (HTFET), line edge/width roughness (LER/LWR), Schmitt–Trigger (ST2) static random access memory (SRAM), sidewall roughness (SWR), surface roughness (SR). I