An Efficient Heterogeneous Register File Implementation for FPGAs

Abstract—For the future of computing, wide usage of hetero-geneous architecture is indispensable since advances in technology scaling cannot satisfy the expected increase in performance of computational platforms anymore. FPGA is a promising platform for heterogeneous computing due to its configurable structure. Each part of an FPGA can be configured to perform a different task that it is best suited for. Such a heterogeneous system needs a common register file (RF) that can serve different parts of the FPGA with at different characteristics in terms of running frequency, data consumption/production rate, required number of ports, data widths, address spaces and endianness. In this study, we propose a heterogeneous register file (HRF) architecture for FPGA-based heterogeneous systems. The designed register file uses a heterogeneous multi-port base-RF to provide such heterogeneity. For the power and area reduction, the design takes advantage of frequency differences between processing elements and HRF by an efficient multi-pumping system. According to the literature, this is the first study on FPGA-based heteroge-neous RFs. For experimentation, HRF is tested in four different heterogeneous architectures with increasing complexity. For all HRF configurations, speed, area and energy are measured. Test results of the HRF on Xilinx Virtex-5 show that our heterogeneous register file outperforms other RF architectures implemented by conventional methods. I